Hybrid ARQ

This paper presents a new type of hybrid ARQ scheme for error control in data communication systems. The new scheme is based on the concept that the parity-check digits for error correction are sent to the receiver only when they are needed. Normally, data blocks with some parity-check bits for error detection are transmitted. When a data block D is detected in errors, the retransmissions are not simply repetitions of D, but alternate repetitions of a parity block P(D) and D. The parity block P(D) is formed based on D and a half-rate invertible code which is capable of correcting r or fewer errors and simultaneously detecting d ( d > r) or fewer errors. When a parity block is received, it is used to recover the originally transmitted data block either by inversion or by decoding operation. The repetitions of the parity block P(D) and the data block D are alternately stored in the receiver buffer for error correction until D is recovered.